1. Field of the Invention
The present invention relates to a semiconductor device comprising a Fin field effect transistor, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Much attention has been paid to a Fin field effect transistor (hereinafter referred to as a “FinFET”) as a transistor characterized by offering a larger ON current and a smaller OFF current than a planar transistor. In the FinFET, a gate electrode is formed to stride across a projecting semiconductor region. A gate insulating film is formed between the gate electrode and the projecting semiconductor region. A part of the projecting semiconductor region immediately under the gate electrode forms a channel region. A part of the projecting semiconductor region which is not covered with the gate electrode forms a source/drain region.
Two types of FinFET are available: a single-structure FinFET with one gate electrode and one channel region, and a multi-structure FinFET with a plurality of gate electrodes and a plurality of channel regions. Japanese Patent Laid-Open No. 64-8670 discloses a single-structure FinFET. Japanese Patent Laid-Open Nos. 2002-118255 and 2001-298194 disclose multi-structure FinFETs.
FIG. 1 illustrates a top view of a semiconductor device including a multi-structure FinFET with two gate electrodes. As illustrated in FIG. 1, the FinFET includes projecting semiconductor region 1 on a substrate. Two gate electrodes 2 are provided so as to stride across semiconductor region 1. A gate insulating film (not illustrated in the drawings) is provided between semiconductor region 1 and each gate electrode 2. Both parts of the semiconductor region 1 sandwiching each gate electrode 2 form source/drain region 3. Semiconductor region 1, one gate electrode 2, the gate insulating film, and source/drain region 3 form one FinFET.
FIGS. 2 to 11 are diagrams illustrating a process of manufacturing a semiconductor device including the FinFET. Each of FIGS. 12 to 20A, 20B, and 20C illustrates sectional views of cross sections of the semiconductor device corresponding to cross sections A-A′, B-B′, and C-C′ in FIG. 1. First, silicon semiconductor substrate 4 is prepared. A surface of silicon semiconductor substrate 4 is oxidized to form silicon oxide film 5. Then, a silicon nitride film is formed all over the resulting surface. A pattern of a photo resist (not illustrated in the drawings) is formed on the silicon nitride film using a lithography technique. The silicon nitride film is thereafter dry etched through the pattern of the photo resist as a mask to form pattern 6 of the silicon nitride film. This step covers silicon semiconductor region (active region) 1 with pattern 6 of the silicon nitride film and forms a shape in which a part of silicon semiconductor substrate 1 corresponding to an isolation region is exposed (FIG. 2).
Then, pattern 6 of the silicon nitride film is used as a hard mask to dry etch silicon oxide film 5 and silicon semiconductor substrate 4. The dry etched part of silicon semiconductor substrate 4 is thereafter oxidized to grow a silicon oxide film. The silicon oxide film is then subjected to a CMP process to form isolation region 7 (FIG. 3).
Then, pattern 6 of the silicon nitride film is removed. A silicon nitride film is newly formed on a part of silicon semiconductor substrate 4 on which isolation region 7 has not been formed. A pattern of a photo resist (not illustrated in the drawings) is thereafter provided using a lithography technique. The silicon nitride film is then dry etched through the pattern of the photo resist as a mask to form mask pattern 8 of the silicon nitride film (FIG. 4). Silicon oxide film 5 is then removed by dry etching using mask pattern 8 of the silicon nitride film as a mask. At the same time, projecting semiconductor region 9 is formed.
In this case, the dry etching may degrade an upper part of projecting semiconductor region 9. Thus, to remove the degraded part, the upper part of projecting semiconductor region 9 is subjected to sacrifice oxidation. The sacrifice oxidation layer (not illustrated in the drawings) is removed by wet etching to expose projecting semiconductor region 9 (FIG. 5). Then, mask pattern 8 of the silicon nitride film is removed by wet etching (FIG. 6).
Subsequently, a surface of projecting semiconductor region 9 is oxidized to form gate insulating film 10 (FIG. 7). DOPOS (DOped POlycrystalline Silicon) is thereafter grown to deposit polysilicon film 11 (FIG. 8).
Then, tungsten film 12 is deposited on polysilicon film 11 to form a gate electrode of silicide. However, if tungsten film 12 is deposited on polysilicon film 11 in this condition, the following silicidization and shaping of the gate electrode will be difficult. Thus, polysilicon film 11 is subjected to the CMP process and thus flattened. Tungsten film 12 is then deposited on polysilicon film 11 (FIG. 9).
Then, the tungsten is silicidized to form a laminate structure of the W/WSi/(polysilicon film). Moreover, mask 13 of a silicon nitride film is formed on the laminate structure of the W/WSi/(polysilicon film). Tungsten film 12 is thereafter removed by the lithography technique using mask 13. Silicon nitride film 14 is then formed all over the resulting surface (FIG. 10).
Thereafter, silicon nitride film 14 and polysilicon film 11 are removed by dry etching using mask 13 to expose a part of projecting semiconductor region 9. Impurities are thereafter ion-implanted into the exposed part of projecting semiconductor region 9 to form a source/drain region. As described above, the FinFET is formed (FIG. 11).
However, according to the related method of manufacturing the semiconductor device including the FinFET, the structure in FIG. 8, described above, includes no stopper when polysilicon film 11 was subjected to the CMP process. Thus, uniformly carrying out the CMP process on the top surface of polysilicon film 11 was difficult. If the top surface of polysilicon film 11 was non-uniform, when metal was deposited on polysilicon film 11 and silicidized to form a gate electrode, the silicidization may have been non-uniform or the gate electrode may have been non-uniformly shaped. As a result, the gate electrode may have been peeled off, or desired characteristics required for the gate electrode may have been difficult to achieve. Furthermore, the silicidization may have developed excessively even into the gate insulating film in some areas, the insulating property of which may thus have been impaired.
I have now discovered that when the CMP process is carried out on the top surface of a material for the gate electrode, the mask pattern is used as a stopper to allow the top surface of the material for the gate electrode to be accurately flattened. I have now discovered that this can solve the above problems.